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» MARS-C: modeling and reduction of soft errors in combination...
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ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 3 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
ISQED
2009
IEEE
103views Hardware» more  ISQED 2009»
14 years 9 hour ago
A systematic approach to modeling and analysis of transient faults in logic circuits
With technology scaling, the occurrence rate of not only single, but also multiple transients resulting from a single hit is increasing. In this work, we consider the effect of th...
Natasa Miskov-Zivanov, Diana Marculescu
DAC
2008
ACM
14 years 6 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
13 years 11 months ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
13 years 10 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...