9 search results - page 2 / 2 » MIRA: A Multi-layered On-Chip Interconnect Router Architectu... |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
TC
2010
13 years 3 months ago
2010
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
DAC
1998
ACM
14 years 5 months ago
1998
ACM
In this paper we present a new global router appropriate for Multichip Module MCM and dense Printed Circuit Board PCB design, which utilizes a hybrid of the classical rip-up and r...