50 search results - page 1 / 10 » MIST - A Design Aid for Programmable Pipelined Processors |
DAC
1994
ACM
13 years 9 months ago
1994
ACM
-- In this paper, a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that m...
ISCA
2003
IEEE
13 years 10 months ago
2003
IEEE
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
FPL
2007
Springer
13 years 11 months ago
2007
Springer
Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock freque...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...