44 search results - page 2 / 9 » MOS VLSI circuit simulation by hardware accelerator using se... |
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract- Analog iterative decoders offer several advantages over their digital counterparts in terms of speed and power -A- log-MAP consumption. The current state of art CMOS anal...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—The linearity of the transconductance stage is of major concern in the design of some analog circuits. In this paper, Volterra series expansion is used to compute the intermodul...
FCCM
2008
IEEE
13 years 11 months ago
2008
IEEE
The recent turmoil in global credit markets has demonstrated the need for advanced modelling of credit risk, which can take into account the effects of changing economic condition...
FCCM
2009
IEEE
13 years 11 months ago
2009
IEEE
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...
FCCM
2006
IEEE
13 years 8 months ago
2006
IEEE
With advances in reconfigurable hardware, especially field-programmable gate arrays (FPGAs), it has become possible to use reconfigurable hardware to accelerate complex applicatio...