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ASPDAC
2010
ACM
137views Hardware» more  ASPDAC 2010»
13 years 1 months ago
Managing verification error traces with bounded model debugging
Managing long verification error traces is one of the key challenges of automated debugging engines. Today, debuggers rely on the iterative logic array to model sequential behavior...
Sean Safarpour, Andreas G. Veneris, Farid N. Najm
TCAD
2010
136views more  TCAD 2010»
12 years 10 months ago
Bounded Model Debugging
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
Brian Keng, Sean Safarpour, Andreas G. Veneris
POPL
2003
ACM
14 years 3 months ago
From symptom to cause: localizing errors in counterexample traces
There is significant room for improving users' experiences with model checking tools. An error trace produced by a model checker can be lengthy and is indicative of a symptom...
Thomas Ball, Mayur Naik, Sriram K. Rajamani
ECBS
2010
IEEE
209views Hardware» more  ECBS 2010»
13 years 8 months ago
Continuous Verification of Large Embedded Software Using SMT-Based Bounded Model Checking
The complexity of software in embedded systems has increased significantly over the last years so that software verification now plays an important role in ensuring the overall pr...
Lucas Cordeiro, Bernd Fischer 0002, João Ma...
ISSTA
2010
ACM
13 years 5 months ago
Analysis of invariants for efficient bounded verification
SAT-based bounded verification of annotated code consists of translating the code together with the annotations to a propositional formula, and analyzing the formula for specifica...
Juan P. Galeotti, Nicolás Rosner, Carlos L&...