85 search results - page 1 / 17 » Mapping Interconnection Networks into VEDIC Networks |
IPPS
1993
IEEE
13 years 9 months ago
1993
IEEE
We show the universality of the VEDIC network in simulating other well known interconnection networks by generating the parameters of the VEDtC network automatically. Algorithms a...
3DIC
2009
IEEE
14 years 2 days ago
2009
IEEE
—The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing Through Silicon Vias (TSV) for vertical connectivity is investigated with a cycle-a...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we explore the use of hierarchically structured multiprocessor tasks (M-tasks) for programming multi-core cluster systems. These systems often have hierarchically s...
SIGCOMM
2012
ACM
11 years 7 months ago
2012
ACM
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case...
DGCI
2005
Springer
13 years 10 months ago
2005
Springer
Due to the restriction of SIMD mode to local operations in VLSI massively parallel vision chips, using programmable connections and asynchronous communications are key ingredients ...