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» Matrix Multiplication on Two Interconnected Processors
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2006
IEEE
13 years 10 months ago
Matrix Multiplication on Two Interconnected Processors
This paper presents a new partitioning algorithm to perform matrix multiplication on two interconnected heterogeneous processors. Data is partitioned in a way which minimizes the ...
Brett A. Becker, Alexey L. Lastovetsky
ERSA
2010
172views Hardware» more  ERSA 2010»
13 years 2 months ago
A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
Heiner Giefers, Marco Platzner
EUROPAR
2009
Springer
13 years 9 months ago
Two-Dimensional Matrix Partitioning for Parallel Computing on Heterogeneous Processors Based on Their Functional Performance Mod
Abstract. The functional performance model (FPM) of heterogeneous processors has proven to be more realistic than the traditional models because it integrates many important featur...
Alexey L. Lastovetsky, Ravi Reddy
PDP
2010
IEEE
13 years 11 months ago
Experimental Study of Six Different Implementations of Parallel Matrix Multiplication on Heterogeneous Computational Clusters of
—Two strategies of distribution of computations can be used to implement parallel solvers for dense linear algebra problems for Heterogeneous Computational Clusters of Multicore ...
Pedro Alonso, Ravi Reddy, Alexey L. Lastovetsky
ASAP
2008
IEEE
118views Hardware» more  ASAP 2008»
13 years 10 months ago
Bit matrix multiplication in commodity processors
Registers in processors generally contain words or, with the addition of multimedia extensions, short vectors of subwords of bytes or 16-bit elements. In this paper, we view the c...
Yedidya Hilewitz, Cédric Lauradoux, Ruby B....