392 search results - page 79 / 79 » Maximal Completion |
HPCA
2012
IEEE
12 years 10 days ago
2012
IEEE
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been...
ISCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Minimizing latency and maximizing throughput are important goals in the design of routing algorithms for interconnection networks. Ideally, we would like a routing algorithm to (a...