5 search results - page 1 / 1 » Meeting Delay Constraints in DSM by Minimal Repeater Inserti... |
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints. We use mini...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
We present a unified framework that considers flipflop and repeater insertion and the placement of flipflop/repeater blocks during RT or higher level design. We introduce the...
ISPD
2000
ACM
13 years 9 months ago
2000
ACM
In this paper we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and der...
ISQED
2010
IEEE
13 years 11 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...