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» Memory Aware High-Level Synthesis for Embedded Systems
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IESS
2007
Springer
128views Hardware» more  IESS 2007»
13 years 11 months ago
An Interactive Design Environment for C-based High-Level Synthesis
: Much effort in RTL design has been devoted to developing “push-button” types of tools. However, given the highly complex nature, and lack of control on RTL design, push-butt...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
DATE
2004
IEEE
210views Hardware» more  DATE 2004»
13 years 9 months ago
Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
13 years 9 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
ICCD
2001
IEEE
124views Hardware» more  ICCD 2001»
14 years 2 months ago
High-Level Power Modeling of CPLDs and FPGAs
In this paper, we present a high-level power modeling technique to estimate the power consumption of reconfigurable devices such as complex programmable logic devices (CPLDs) and ...
Li Shang, Niraj K. Jha
SIGSOFT
2006
ACM
13 years 11 months ago
Bit level types for high level reasoning
Bitwise operations are commonly used in low-level systems code to access multiple data fields that have been packed into a single word. Program analysis tools that reason about s...
Ranjit Jhala, Rupak Majumdar