31 search results - page 3 / 7 » Memory Consistency and Process Coordination for SPARC Multip... |
FPL
2005
Springer
13 years 10 months ago
2005
Springer
A parallel MPEG-4 Simple Profile encoder for FPGA based multiprocessor System-on-Chip (SOC) is presented. The goal is a computationally scalable framework independent of platform....
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
SOSP
1997
ACM
13 years 6 months ago
1997
ACM
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...