Sciweavers

27 search results - page 4 / 6
» Memory Organization with Multi-Pattern Parallel Accesses
Sort
View
ISCAPDCS
2001
13 years 6 months ago
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
This paper presents the evaluation of a non-blocking, decoupled memory/execution, multithreaded architecture known as the Scheduled Dataflow (SDF). The major recent trend in digit...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 2 days ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
FTCS
1993
123views more  FTCS 1993»
13 years 6 months ago
Fast, On-Line Failure Recovery in Redundant Disk Arrays
This paper describes and evaluates two algorithms for performing on-line failure recovery (data reconstruction) in redundant disk arrays. It presents an implementation of disk-ori...
Mark Holland, Garth A. Gibson, Daniel P. Siewiorek
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 2 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
HPCA
1998
IEEE
13 years 9 months ago
The Effectiveness of SRAM Network Caches in Clustered DSMs
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...
Adrian Moga, Michel Dubois