Sciweavers

Share
7 search results - page 1 / 2
» Memory aware compilation through accurate timing extraction
Sort
View
DAC
2000
ACM
13 years 2 months ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
MICRO
2002
IEEE
104views Hardware» more  MICRO 2002»
12 years 6 months ago
Compiling for instruction cache performance on a multithreaded architecture
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
Rakesh Kumar, Dean M. Tullsen
PERVASIVE
2007
Springer
12 years 7 months ago
Movement-Based Group Awareness with Wireless Sensor Networks
We propose a method through which dynamic sensor nodes determine that they move together, by communicating and correlating their movement information. We describe two possible solu...
Raluca Marin-Perianu, Mihai Marin-Perianu, Paul J....
CASES
2010
ACM
11 years 11 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
COMPSAC
2009
IEEE
12 years 6 months ago
Towards a Next-Generation Matrix Library for Java
Matrices are essential in many fields of computer science, especially when large amounts of data must be handled efficiently. Despite this demand for matrix software, we were una...
Holger Arndt, Markus Bundschus, Andreas Naegele
books