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DAC
2000
ACM

Memory aware compilation through accurate timing extraction

13 years 22 days ago
Memory aware compilation through accurate timing extraction
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this bottleneck. However, such features can not be efficiently exploited in processor-based embedded systems without memory-aware compiler support. We describe a memory-aware compiler approach that exploits such efficient memory access modes by extracting accurate timing information, allowing the compiler's scheduler to perform global code reordering to better hide the latency of memory operations. Our memory-aware compiler scheduled several benchmarks on the TI C6201 processor architecture interfaced with a 2-bank synchronous DRAM and generated average improvements of ~24% over the best possible schedule using a traditional (memory-transparent) optimizing compiler, demonstrating the utility of our memory-aware compilation approach.
Peter Grun, Nikil D. Dutt, Alexandru Nicolau
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2000
Where DAC
Authors Peter Grun, Nikil D. Dutt, Alexandru Nicolau
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