7 search results - page 1 / 2 » Memory aware compilation through accurate timing extraction |
DAC
2000
ACM
14 years 5 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
MICRO
2002
IEEE
13 years 9 months ago
2002
IEEE
Instruction cache aware compilation seeks to lay out a program in memory in such a way that cache conflicts between procedures are minimized. It does this through profile-driven...
PERVASIVE
2007
Springer
13 years 10 months ago
2007
Springer
We propose a method through which dynamic sensor nodes determine that they move together, by communicating and correlating their movement information. We describe two possible solu...
CASES
2010
ACM
13 years 2 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
COMPSAC
2009
IEEE
13 years 9 months ago
2009
IEEE
Matrices are essential in many fields of computer science, especially when large amounts of data must be handled efficiently. Despite this demand for matrix software, we were una...