36 search results - page 6 / 8 » Memory bank aware dynamic loop scheduling |
TVLSI
2008
13 years 5 months ago
2008
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
IPPS
2010
IEEE
13 years 3 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
ICASSP
2010
IEEE
13 years 5 months ago
2010
IEEE
The latest communication technologies invariably consist of modules with dynamic behavior. There exists a number of design tools for communication system design with their foundat...