24 search results - page 4 / 5 » Memory hierarchy reconfiguration for energy and performance ... |
TPDS
2008
13 years 5 months ago
2008
Multicore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern app...
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
LCTRTS
2010
Springer
14 years 13 days ago
2010
Springer
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
ISLPED
2003
ACM
13 years 11 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
CODES
2001
IEEE
13 years 9 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...