88 search results - page 4 / 18 » Memory models: a case for rethinking parallel languages and ... |
ASPLOS
2006
ACM
13 years 11 months ago
2006
ACM
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...
ACMMSP
2006
ACM
13 years 11 months ago
2006
ACM
Many people have proposed adding transactions, or atomic blocks, to type-safe high-level programming languages. However, researchers have not considered the semantics of transacti...
SIGARCH
2008
13 years 5 months ago
2008
This paper presents the OpenDF framework and recalls that dataflow programming was once invented to address the problem of parallel computing. We discuss the problems with an impe...
EURODAC
1994
IEEE
13 years 10 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
CORR
2006
Springer
13 years 5 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...