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» Memory-aware NoC Exploration and Design
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DATE
2004
IEEE
158views Hardware» more  DATE 2004»
13 years 9 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
13 years 11 months ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
NOCS
2007
IEEE
13 years 11 months ago
Fast, Accurate and Detailed NoC Simulations
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
Pascal T. Wolkotte, Philip K. F. Hölzenspies,...
SAMOS
2005
Springer
13 years 10 months ago
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chi...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...
JSA
2007
123views more  JSA 2007»
13 years 5 months ago
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Ch...
Holger Blume, Thorsten von Sydow, Daniel Becker, T...