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» Methodology to Evaluate the Functionality of Specification L...
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VLSID
2002
IEEE
189views VLSI» more  VLSID 2002»
14 years 5 months ago
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, ...
HICSS
2007
IEEE
181views Biometrics» more  HICSS 2007»
13 years 11 months ago
A Methodology to Evaluate Agent Oriented Software Engineering Techniques
Systems using Software Agents (or Multi-Agent Systems, MAS) are becoming more popular within the development mainstream because, as the name suggests, an Agent aims to handle task...
Chia-En Lin, Krishna M. Kavi, Frederick T. Sheldon...
SAC
1998
ACM
13 years 9 months ago
A specification language for the WIDE workflow model
This paper presents a workflow specification language developed in the WIDE project. The language provides a rich organisation model, an information model including presentation d...
Daniel K. C. Chan, Jochem Vonk, Gabriel Sanchez, P...
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 9 months ago
Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to ...
Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Aze...
DT
2006
180views more  DT 2006»
13 years 5 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...