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» Methodology to achieve higher tolerance to delay variations ...
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ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie
ISLPED
2006
ACM
129views Hardware» more  ISLPED 2006»
13 years 11 months ago
Variation-driven device sizing for minimum energy sub-threshold circuits
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
Joyce Kwong, Anantha P. Chandrakasan
ASYNC
2007
IEEE
131views Hardware» more  ASYNC 2007»
13 years 11 months ago
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia...
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
14 years 5 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
SIGCOMM
2004
ACM
13 years 10 months ago
A wavelet-based approach to detect shared congestion
Per-flow congestion control helps endpoints fairly and efficiently share network resources. Better utilization of network resources can be achieved, however, if congestion manag...
Min Sik Kim, Taekhyun Kim, YongJune Shin, Simon S....