33 search results - page 1 / 7 » Micro Architecture Coverage Directed Generation of Test Prog... |
DAC
1999
ACM
14 years 5 months ago
1999
ACM
IFIP
2001
Springer
13 years 9 months ago
2001
Springer
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Functional verification of microprocessors is one of the most complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validatio...
CODES
2008
IEEE
13 years 6 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...