4 search results - page 1 / 1 » Minimizing Power Dissipation in Non-Zero Skew-Based Clock Di... |
ISCAS
1995
IEEE
13 years 8 months ago
1995
IEEE
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
INTEGRATION
2007
13 years 4 months ago
2007
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...