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LCTRTS
2010
Springer
13 years 11 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
CASES
2006
ACM
13 years 8 months ago
Minimizing bank selection instructions for partitioned memory architecture
Bernhard Scholz, Bernd Burgstaller, Jingling Xue
TECS
2008
70views more  TECS 2008»
13 years 4 months ago
Minimal placement of bank selection instructions for partitioned memory architectures
Bernhard Scholz, Bernd Burgstaller, Jingling Xue
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
13 years 8 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu
ICASSP
2008
IEEE
13 years 11 months ago
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
Chun Jason Xue, Tiantian Liu, Zili Shao, Jingtong ...