36 search results - page 2 / 8 » Miss reduction in embedded processors through dynamic, power... |
CASES
2008
ACM
13 years 6 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
SBCCI
2009
ACM
13 years 11 months ago
2009
ACM
We present an application-driven customization methodology for energy-efficient inter-core communication in embedded multiprocessors. The methodology leverages configurable cach...
DSD
2006
IEEE
13 years 8 months ago
2006
IEEE
Title of thesis: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering Alokika Dash, Master of Science, 2006 Thesis dire...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
ARCS
2006
Springer
13 years 8 months ago
2006
Springer
As applications tend to grow more complex and use more memory, the demand for cache space increases. Thus embedded processors are inclined to use larger caches. Predicting a miss i...