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2008
ACM

Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

9 years 3 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral circuits, which according to recent studies account for a considerable amount of cache leakage. At circuit level, we propose a novel design with multiple sleep modes for cache peripherals. Each mode represents a trade-off between leakage reduction and wakeup delay. Architectural control is proposed to decide "when and how" to use these different low-leakage modes using cache miss information to guide its action. This control is based on simple state machines that do not impact area or power consumption and can thus be used even in the resource constrained processors. Experimental results indicate that proposed techniques can keep the L1 cache peripherals in one of the low-power modes for more than 85% of total execution time, on average. This translates to an average leakage power reduction of 50% for ...
Houman Homayoun, Mohammad A. Makhzan, Alexander V.
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where CASES
Authors Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum
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