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    » Mixing buffers and pass transistors in FPGA routing architec...
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    FPGA
    2001
    ACM
    123views FPGA» more  FPGA 2001»
    Mixing buffers and pass transistors in FPGA routing architectures
    13 years 9 months ago
    Mixing buffers and pass transistors in FPGA routing architectures
    Download  www.eecg.toronto.edu
    The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
    Mike Sheng, Jonathan Rose
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    FPGA
    1999
    ACM
    155views FPGA» more  FPGA 1999»
    FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
    13 years 9 months ago
    FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density
    Download  www.eecg.toronto.edu
    In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
    Vaughn Betz, Jonathan Rose
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    TVLSI
    2008
    106views more  TVLSI 2008»
    New Non-Volatile Memory Structures for FPGA Architectures
    13 years 4 months ago
    New Non-Volatile Memory Structures for FPGA Architectures
    Download  www.ee.ucla.edu
    A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is describ...
    David Choi, Kyu Choi, John D. Villasenor
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    FPGA
    2000
    ACM
    161views FPGA» more  FPGA 2000»
    The effect of LUT and cluster size on deep-submicron FPGA performance and density
    13 years 8 months ago
    The effect of LUT and cluster size on deep-submicron FPGA performance and density
    Download  www.eecg.toronto.edu
    In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...
    Elias Ahmed, Jonathan Rose
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