19 search results - page 1 / 4 » Mobile Memory: Improving Memory Locality in Very Large Recon... |
FCCM
2002
IEEE
13 years 10 months ago
2002
IEEE
ERSA
2010
13 years 3 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
ACSC
2004
IEEE
13 years 9 months ago
2004
IEEE
Matrix multiplication is a basic computing operation. Whereas it is basic, it is also very expensive with a straight forward technique of O(N3 ) runtime complexity. More complex s...
DATE
2008
IEEE
14 years 6 days ago
2008
IEEE
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...