Among the many techniques for system-level power management, it is not currently possible to guarantee timing constraints and have a comprehensive system model at the same time. S...
Abstract. Power efficiency has become a key design trade-off in embedded system designs. For system-on-a-chip embedded systems, an external bus interconnects embedded processor co...
Therequirementsfor amain memorydatastoragemodel are both compactnessand efficient processing for all database operations. The DBGraph storage model, proposed in this paper, achiev...
Studies of the fault-tolerance of graphs have tended to largely concentrate on classical graph connectivity. This measure is very basic, and conveys very little information for des...
Vijay Lakamraju, Zahava Koren, Israel Koren, C. Ma...
In this paper we present an improved scheduling technique for the synthesis of time-triggered embedded systems. Our system model captures both the flow of data and that of control...