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MTV
2003
IEEE
109views Hardware» more  MTV 2003»
13 years 10 months ago
A Methodology for Validation of Microprocessors using Equivalence Checking
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Nikil D. Dutt
ITC
1998
IEEE
95views Hardware» more  ITC 1998»
13 years 9 months ago
Native mode functional test generation for processors with applications to self test and design validation
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
Jian Shen, Jacob A. Abraham
MTV
2005
IEEE
81views Hardware» more  MTV 2005»
13 years 11 months ago
Search-Space Optimizations for High-Level ATPG
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architec...
Jorge Campos, Hussain Al-Asaad
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 9 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...