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» Model Checking Verilog Descriptions of Cell Libraries
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CATA
2010
13 years 5 months ago
A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
Bahram Hakhamaneshi, Behnam S. Arad
FPGA
2004
ACM
174views FPGA» more  FPGA 2004»
13 years 10 months ago
A compiled accelerator for biological cell signaling simulations
The simulation of large systems of biochemical reactions is a key part of research into molecular signaling and information processing in biological cells. However, it can be impr...
John F. Keane, Christopher Bradley, Carl Ebeling
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
13 years 9 months ago
On the Design and Verification Methodology of the Look-Aside Interface
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
Ali Habibi, Asif Iqbal Ahmed, Otmane Aït Moha...
PACT
2005
Springer
13 years 11 months ago
Optimal Behavior of a Moving Creature in the Cellular Automata Model
The goal of our investigation is to find automatically the best rule for a cell in the cellular automata model. The cells are either of type Obstacle, Empty or Creature. Only Crea...
Mathias Halbach, Rolf Hoffmann
ACRI
2004
Springer
13 years 10 months ago
Optimizing the Behavior of a Moving Creature in Software and in Hardware
We have investigated a problem where the goal is to find automatically the best rule for a cell in the cellular automata model. The cells are either of type OBSTACLE, EMPTY or CRE...
Mathias Halbach, Wolfgang Heenes, Rolf Hoffmann, J...