24 search results - page 1 / 5 » Model Order Reduction of Large Circuits Using Balanced Trunc... |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a statespace model where t...
DAC
2007
ACM
13 years 9 months ago
2007
ACM
RLC circuits have been shown to be better formulated as second-order systems instead of first-order systems. The corresponding model order reduction techniques for secondorder sys...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
- This paper presents a spectrally-weighted balanced truncation technique for RLC interconnects, a technique needed when the interconnect circuit parameters change as a result of v...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...