Model Order Reduction of Large Circuits Using Balanced Truncation

A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order of circuits before circuit-level simulation. In contrast to Padebased algorithms which match the reduced order system with original system in some given frequencies, balanced realization based model algorithms provide a nearly optimal matching over all frequencies. Hence the balanced realization method produces stable and more accurate results compared to the Pade-based algorithms for model reduction. In addition given an upper bound for error, it is possible to compute the minimum degree for the reduced order model a priori. A numerically efficient method for balanced truncation of large circuits using the Arnoldi algorithm is presented and experimental results are reported.

• Type: Conference
• Year: 1999
• Where: ASPDAC
• Authors: Payam Rabiei, Massoud Pedram
• Keywords: ASPDAC 1999, Balanced Realization, Hardware, Large Circuits, Model Order Reduction