288 search results - page 1 / 58 » Model checking SystemC designs using timed automata |
CODES
2008
IEEE
13 years 6 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
—SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems rent levels of abstraction. The SystemC standard permits simulato...
FMSD
2006
13 years 5 months ago
2006
Two base algorithms are known for reachability verification over timed automata. They are called forward and backwards, and traverse the automata edges using either successors or p...
IJCSA
2007
13 years 5 months ago
2007
Timed Concurrent State Machines are an application of Alur’s Timed Automata concept to coincidence-based (rather than interleaving) CSM modeling technique. TCSM support the idea...
ATVA
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. Priorities are often used to resolve conflicts in timed systems. However, priorities are not directly supported by state-of-art model checkers. Often, a designer has to ...