356 search results - page 3 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
HPCA
2005
IEEE
14 years 5 months ago
2005
IEEE
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
IEEEPACT
2009
IEEE
13 years 12 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
HIPEAC
2009
Springer
13 years 9 months ago
2009
Springer
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
EUROPAR
1997
Springer
13 years 9 months ago
1997
Springer
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...