32 search results - page 2 / 7 » Modeling Multiprocessor Cache Protocol Impact on MPI Perform... |
ISCA
1993
IEEE
13 years 9 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
ISCA
1993
IEEE
13 years 9 months ago
1993
IEEE
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
Parallel programs that modify shared data in a cachecoherent multiprocessor with a write-invalidate coherence protocol create ownership overhead in the form of ownership acquisiti...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
ISOLA
2010
Springer
13 years 3 months ago
2010
Springer
This article comprehensively surveys the work accomplished during the past decade on an approach to analyze concurrent systems qualitatively and quantitatively, by combining functi...