71 search results - page 14 / 15 » Modeling and Simulating Memory Hierarchies in a Platform-Bas... |
DAC
2005
ACM
14 years 6 months ago
2005
ACM
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
SPAA
2006
ACM
13 years 11 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) techniq...
ISPASS
2010
IEEE
14 years 5 days ago
2010
IEEE
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to m...