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» Modeling and Synthesis of Hardware-Software Morphing
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CODES
2007
IEEE
13 years 11 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
CODES
2006
IEEE
13 years 11 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
CODES
2005
IEEE
13 years 11 months ago
Automatic network generation for system-on-chip communication design
With growing system complexities, system-level communication design is becoming increasingly important and advanced, network-oriented communication architectures become necessary....
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
CODES
2006
IEEE
13 years 11 months ago
Automatic generation of transaction level models for rapid design space exploration
Transaction-level modeling has been touted to improve simulation performance and modeling efficiency for early design space exploration. But no tools are available to generate suc...
Dongwan Shin, Andreas Gerstlauer, Junyu Peng, Rain...
CODES
2006
IEEE
13 years 11 months ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...