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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
13 years 12 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
13 years 11 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
13 years 3 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt
SECON
2010
IEEE
13 years 3 months ago
Coexistence-Aware Scheduling for Wireless System-on-a-Chip Devices
Abstract--Today's mobile devices support many wireless technologies to achieve ubiquitous connectivity. Economic and energy constraints, however, drive the industry to impleme...
Lei Yang, Vinod Kone, Xue Yang, York Liu, Ben Y. Z...
IJCNN
2000
IEEE
13 years 10 months ago
A 2D Neuromorphic VLSI Architecture for Modeling Selective Attention
Selectiveattentionis a mechanismsused to sequentiallyselectthe spatiallocationsof salientregionsin the sensor’sfieldof view. This mechanism overcomesthe problem of flooding limi...
Giacomo Indiveri