10 search results - page 1 / 2 » Multi-bit Error Tolerant Caches Using Two-Dimensional Error ... |
MICRO
2007
IEEE
13 years 11 months ago
2007
IEEE
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
ISCA
2010
IEEE
13 years 9 months ago
2010
IEEE
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
SC
2009
ACM
13 years 11 months ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
VTS
2007
IEEE
13 years 11 months ago
2007
IEEE
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...