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ISPD
2000
ACM
131views Hardware» more  ISPD 2000»
13 years 9 months ago
Multi-center congestion estimation and minimization during placement
As technology advances, more and more issues need to be considered in the placement stage, e.g., wirelength, congestion, timing, coupling. It is very hard to consider all of them ...
Maogang Wang, Xiaojian Yang, Kenneth Eguro, Majid ...
ISPD
1999
ACM
108views Hardware» more  ISPD 1999»
13 years 9 months ago
On the behavior of congestion minimization during placement
Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability accurately. In thi...
Maogang Wang, Majid Sarrafzadeh
ICCAD
2008
IEEE
97views Hardware» more  ICCAD 2008»
14 years 1 months ago
Guiding global placement with wire density
—This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifie...
Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Bala...
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
13 years 11 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 1 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok