41 search results - page 2 / 9 » Multi-voltage floorplan design with optimal voltage assignme... |
ISPD
1999
ACM
13 years 9 months ago
1999
ACM
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
ISLPED
2004
ACM
13 years 10 months ago
2004
ACM
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
This paper proposes Noise-Direct, a design methodology for power integrity aware floorplanning, using microarchitectural feedback to guide module placement. Stringent power constr...