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» Multiobjective VLSI cell placement using distributed genetic...
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ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 9 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
IPPS
2003
IEEE
13 years 10 months ago
Parallel Tabu Search in a Heterogeneous Environment
In this paper, we discuss a parallel tabu search algorithm with implementation in a heterogeneous environment. Two parallelization strategies are integrated: functional decomposit...
Ahmad A. Al-Yamani, Sadiq M. Sait, Hassan Barada, ...
ISPD
2003
ACM
105views Hardware» more  ISPD 2003»
13 years 10 months ago
Partition-driven standard cell thermal placement
The thermal problem has been emerged as one of the key issues for next-generation IC design. In this paper, we propose a scheme to achieve better thermal distribution for partitio...
Guoqiang Chen, Sachin S. Sapatnekar
ISPD
2007
ACM
151views Hardware» more  ISPD 2007»
13 years 6 months ago
Pattern sensitive placement for manufacturability
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
Shiyan Hu, Jiang Hu
DATE
2008
IEEE
132views Hardware» more  DATE 2008»
13 years 11 months ago
Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting
Power gating is one of the most effective techniques in reducing the standby leakage current of VLSI circuits. In this paper we introduce a new approach for sleep transistor sizin...
Ehsan Pakbaznia, Massoud Pedram