94 search results - page 1 / 19 » Multiple-banked register file architectures |
IPPS
1996
IEEE
13 years 9 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
The storage for speculative values in superscalar processors is one of the main sources of complexity and power dissipation. In this paper, we present a novel technique to reduce ...
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper investigates the impact of the local and global register file architecture on a reconfigurable system based on the ADRES architecture [3]. The register files consume a s...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...