5 search results - page 1 / 1 » Multiplier energy reduction through bypassing of partial pro... |
APCCAS
2002
IEEE
13 years 9 months ago
2002
IEEE
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
ISLPED
1996
ACM
13 years 9 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
ASAP
2007
IEEE
13 years 6 months ago
2007
IEEE
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...