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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 7 days ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
IPPS
2006
IEEE
13 years 11 months ago
Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
Riad Ben Mouhoub, Omar Hammami
ICRA
2000
IEEE
136views Robotics» more  ICRA 2000»
13 years 10 months ago
Registration of Range Data Using a Hybrid Simulated Annealing and Iterative Closest Point Algorithm
The need to register data is abundant in applications such as: world modeling, part inspection and manufacturing, object recognition, pose estimation, robotic navigation, and reve...
Jason P. Luck, Charles Q. Little, William Hoff
CODES
2009
IEEE
13 years 10 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...