84 search results - page 17 / 17 » NBTI-Aware Synthesis of Digital Circuits |
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
ISPD
2010
ACM
14 years 6 days ago
2010
ACM
In the nanometer IC design, dummy fill is often performed to improve layout pattern uniformity and the post-CMP quality. However, filling dummies might greatly increase intercon...
ISPD
2009
ACM
14 years 5 days ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
RSP
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes the early analysis and estimation features currently implemented in the Berkeley Emulation Engine (BEE) system. BEE is an integrated rapid prototyping and des...