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» NRG: global and detailed placement
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DAC
2007
ACM
14 years 6 months ago
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literatur...
Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang
VIS
2007
IEEE
199views Visualization» more  VIS 2007»
14 years 6 months ago
Topology, Accuracy, and Quality of Isosurface Meshes Using Dynamic Particles
Abstract-This paper describes a method for constructing isosurface triangulations of sampled, volumetric, three-dimensional scalar fields. The resulting meshes consist of triangles...
Miriah Meyer, Robert M. Kirby, Ross Whitaker
ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
13 years 11 months ago
Wire Planning with Bounded Over-the-Block Wires
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...
Hua Xiang, I-Min Liu, Martin D. F. Wong
FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
13 years 10 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
SLIP
2005
ACM
13 years 11 months ago
Congestion prediction in early stages
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...
Chiu-Wing Sham, Evangeline F. Y. Young