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» Nanometer Device Scaling in Subthreshold Circuits
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DATE
2005
IEEE
128views Hardware» more  DATE 2005»
13 years 11 months ago
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhij...
DAC
2004
ACM
14 years 6 months ago
Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant e
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
Anirban Basu, Sheng-Chih Lin, Vineet Wason, Amit M...
ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
13 years 11 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
ISCAS
2002
IEEE
85views Hardware» more  ISCAS 2002»
13 years 10 months ago
A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect
We present a CMOS circuit that utilizes the back-gate effect to extend the linear range of a subthreshold MOS transconductor. Previous designs of wide-linear-range transconductors...
Reid R. Harrison
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
13 years 9 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge