Sciweavers

14 search results - page 3 / 3
» Navigating registers in placement for clock network minimiza...
Sort
View
FPGA
2008
ACM
146views FPGA» more  FPGA 2008»
13 years 6 months ago
FPGA-optimised high-quality uniform random number generators
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
David B. Thomas, Wayne Luk
DAC
1996
ACM
13 years 9 months ago
Glitch Analysis and Reduction in Register Transfer Level
: We presentdesign-for-low-power techniques based on glitch reduction for register-transfer level circuits. We analyze the generation and propagation of glitches in both the contro...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
ENTCS
2008
83views more  ENTCS 2008»
13 years 5 months ago
Elastic Flow in an Application Specific Network-on-Chip
A Network-on-Chip (NoC) is increasingly needed to interconnect the large number and variety of Intellectual Property (IP) cells that make up a System-on-Chip (SoC). The network mu...
Daniel Gebhardt, Kenneth S. Stevens
MOBISYS
2008
ACM
14 years 4 months ago
Composcan: adaptive scanning for efficient concurrent communications and positioning with 802.11
Using 802.11 concurrently for communications and positioning is problematic, especially if location-based services (e.g., indoor navigation) are concurrently executed with real-ti...
Mikkel Baun Kjærgaard, Thomas King